In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly. In order to save efforts to maintain the clock skew issue, the VIA driver provides some options to adjust DPA settings.

Option "DPASetting_DVP0" "int1, int2, int3"

This option is to adjust the clock of DVP0. Int1 ranges from 0 to 15, int2/int3 ranges from 0 to 3.

Option "DPASetting_DVP1" "int1, int2, int3"

This option is to adjust the clock of DVP1. Int1 ranges from 0 to 15, int2/int3 ranges from 0 to 3.

Option "DPASetting_DFPHIGH" "integer"

This option is to adjust the clock of DFP High. The value ranges from 0 to 15.

Option "DPASetting_DFPLOW" "integer"

This option is to adjust the clock of DFP Low. The value ranges from 0 to 15.

Option "DPASetting_VT1636" "int1, int2 "

This option is to adjust the clock of the LVDS transmitter VT1636. Int1 ranges from 0 to 31, and int2 ranges from 0 to 15.