In circuit designs, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly. In order to save efforts to maintain the clock skew issue, the VIA driver provides some options to adjust DPA settings.

The following options apply to LCD, DVI, TV. You can add the options to the related Monitor section to adjust clock.

Option "ClockPolarity" "integer"

This option is to adjust the polarity of DI port clock. Valid values are 0, 1.

Option "ClockAdjust" "integer"

This option is to adjust the value of DI port clock. The value ranges from 0 to 7.

Option "ClockDrivingSelection" "integer"

This option applies to DVP0 and DVP1. The value ranges from 0 to 3.

Option "DataDrivingSelection" "integer"

This option applies to DVP0 and DVP1. The value ranges from 0 to 3.

The following two options apply to LCD panel, which is connected by an external LVDS transmitter. You can add the options to the Monitor section of LCD to adjust clock.

Option "Vt1636ClockSelST1" "integer"

This option is to adjust the DPA values of a LVDS transmitter VT1636. The value ranges from 0 to 31.

Option "Vt1636ClockSelST2" "integer"

This option is to adjust the DPA values of a LVDS transmitter VT1636. The value ranges from 0 to 15.

The option below applies to TV, which is connected by an external TV encoder. You can add this option to the Monitor section of TV to adjust clock.

Option "TvEncoderDPA" "integer"

This option is to adjust the DPA values of a TV encoder VT1625. The value ranges from 0 to 15.